1. Field of the Invention
The present invention relates to a semiconductor having a Lightly Doped Drain structure (hereinafter referred to as a LDD structure) capable of being formed with a high density, more particularly to a gate structure of a semiconductor memory such as a Static Random Access Memory (hereinafter referred to as a SRAM) exhibiting little soft errors.
2. Description of the Related Art
The semiconductor memory is composed of a memory cell array including memory cells arranged in a matrix fashion and a peripheral circuit which controls an operation to record and read out data to/from the memory cell. The conception figure of the semiconductor memory is shown in FIG. 1. Transistors which are formed in the semiconductor memory and used for the uses other than particular ones are constituted such that they have the same size and structure to simplify manufacturing steps, without depending on whether they constitute the memory cell or the peripheral circuit.
Referring to FIGS. 2 and 3, the conventional technologies will be described. FIG. 2 is a part of the conventional semiconductor memory, which is a sectional view showing a MOS region of a memory cell driver disposed in the memory cell area A of a SRAM and NMOS and PMOS regions of a peripheral circuit area B thereof. FIG. 3 is a circuit diagram of a SRAM cell of an enhanced resistor type (hereinafter referred to as an E/R type). As shown in FIG. 2, a P well 2 and a N well 3 are formed in a surface region of a semiconductor substrate 1 which is formed of silicon. A field oxide film (SiO.sub.2) 4 is formed on the surface of the substrate 1, which is a region serving to electrically separate adjacent elements. The memory cell area A and the peripheral circuit area B are formed in the semiconductor substrate 1. Driver transistors Q1 and Q2 are formed in the memory cell area A. A N-channel transistor NMOS and a P-channel PMOS transistor are formed in the peripheral circuit area B.
In the P well 2 of the memory cell area A, formed are an N.sup.+ diffusion region 16 used for source/drain regions and an N.sup.- diffusion region 11 serving as an LDD region, which is overlapped with the N.sup.+ diffusion region 16 and has a tip portion protruding from the N.sup.+ diffusion region 16. In the peripheral circuit area B, formed are an N+ diffusion region 16 used for source/drain regions and an N.sup.- diffusion region 11 serving as an LDD region, which is overlapped with the N.sup.- diffusion layer 16 and has a tip portion protruding from the N.sup.+ diffusion layer 16. An N.sup.+ diffusion region 19 used for source/drain regions of the P-channel transistor PMOS is formed in the N well 3. A gate oxide film 5 is formed in the surface of the semiconductor substrate 1. A gate 71 formed of such as polysilicon is formed on the gate oxide film 5 of the memory cell area A, as well as between the source/drain regions 16 facing each other. Each of the foregoing driver transistors Q1 and Q2 is constituted by the gate 71 and the source/drain regions 16. A side wall insulating film 13 formed of a silicon oxide film is formed on the side surface of the gate 71. In the periphery circuit portion B, the gate 72 formed of such as polysilicon is formed on a gate oxide film 5 which is disposed on the P well 2, as well as between the N type source/drain regions 16 facing each other. The foregoing N channel transistor NMOS is constituted by the gate 72 and the source/drain regions 16. The side wall insulating film 13 is formed on the side surface of the gate 72.
In the peripheral circuit B, a gate 73 is formed of such as polysilicon on the gate oxide film 5 disposed on the N well 3, as well as between the P type source/drain regions 19 facing each other. The foregoing P channel transistor PMOS is constituted by the gate 73 and the source/drain regions 19. The side wall insulating film 13 formed of a silicon oxide film is formed on the side wall of the gate 73. The transistors formed on the semiconductor substrate 1 are covered with a first interlayer insulating film 20 formed of such as SiO2 which is formed by a Chemical Vapor Deposition (hereinafter referred to as a CVD) method. The surface of the interlayer insulting film 20 is flattened by a Chemical Mechanical Polishing (herein after referred to as a CMP) or the like, and a polysilicon wiring 21 is formed on the flattened surface of the interlayer insulating film 20. The polysilicon wiring 21 constitutes resistors R1 and R2 of the SRAM shown in FIG. 3. A second interlayer insulating film 22 formed of SiO2 or the like formed by the CVD method is formed on the first interlayer insulating film 20 so as to cover the polysilicon wiring 21. The surface of the second interlayer insulating film 22 is flattened by the CMP treatment and the like, and a metal wiring 23 formed of aluminum or the like is formed on the flattened surface of the interlayer insulating film 22. A protection insulating film 24 formed of BPSG (Boron-doped Phosphorus Silicate Glass) or the like is formed on the semiconductor substrate 1 so as to cover the metal wiring 23.
FIG. 3 is a circuit diagram of the E/R type SRAM cell. The memory cell of the SRAM stores data in a state which charges at two nodes 1 and 2, each of which is connected to the gate 71 of the corresponding transistors Q1 and Q2 of the memory cell driver. For example, when a potential at the node 1 is at a high level and the node 2 is at a low level, the memory cell indicates "0" data state. Alternately, when the node 1 is at a low level and the node 2 is at a high level, the memory cell indicates "1" data state (see FIG. 9). The charges at the node 1 where it is high in level are stored in a capacitor of a MOS structure which is constituted by the gate 71, gate oxide film 5, semiconductor substrate 1 of the driver transistors Q1 and Q2 connected to the corresponding nodes 1 and 2. Specifically, this capacitor has a structure that uses the gate oxide film as a dielectric and the gate and the semiconductor substrate as an electrode. This capacitor is more stable as its capacitance becomes larger. The reason of this is as follows. Since the amount of the charges stored in the capacitor is large when the capacitance thereof is large, the data do not come to be broken even when the charges stored in the capacitor reduces by external factors.
However, the recent miniaturization of the semiconductor devices leads to also a reduction in an area of a gate of the driver transistors Q1 and Q2, so that the capacitance of the foregoing capacitor actually reduces more and more. The reduction in the capacitance of the capacitor produces an increase in a soft error ratio created by .alpha. ray and the like, resulting in a severe problem to reduce reliability of a system on which the semiconductor devices such as SRAMs are mounted. Concretely, the following phenomenon occurs. When the .alpha. ray is entered onto the vicinity of the gate of the driver transistor, minority carriers of an opposite type to the charges stored in the gate are generated in the incidence portion of the .alpha. ray. The minority carriers combine with the stored charges, whereby the charges reduce. Upon a reduction in the charge, a threshold value of the driver transistor comes to reduce, leading to a undesirable inversion of data latched in the driver transistor. This phenomenon is called a soft error.
For the SRAMs, the transistors constituting the peripheral circuit thereof is required to operate at a high speed. Therefore, the gates of the transistors of the peripheral circuit have a tendency to be smaller. On the other hand, for the memory cell area, unlike the peripheral circuit area, a high operation performance is not required, but a large capacitance of the capacitor is required.
However, setting the gate length of the driver transistors to be large in order to secure the large capacitance of the capacitors is not necessarily a good idea. As shown in FIG. 2 since the driver transistors Q1 and Q2 share the source/drain regions, a distance between transistors Q1 and Q2 is small. Therefore, a limitation to a precision of lithography processes for making the gates of the driver transistors degrades a precision in making the gates thereof. For the reason described above, securing the capacitance of the capacitors of the driver transistors in the memory cell area without degrading the precision in making the gates thereof is a key to the miniaturization of SRAMs and the like.